A field programmable gate array (FPGA) consists of a matrix of programmable logic cells and programmable routing between the programmable logic cells. Each logic cell typically contains various electronic components such as static RAM cells, multiplexers and flip-flops. The functionality of each logic cell may be programmed by writing to the static ram cells and changing the internal configuration of the logic cell.
Similarly, the logic cells within the FPGA are also connected to each other by programmable connection points (e.g. static RAM cells or antifuse points) to allow programmable routing. By writing to these static ram cells, the routing between logic cells may be programmed, and the configuration of the FPGA determined.
Initially, first generation FPGA's were well-suited to implement random logic circuits. A random logic circuit is a collection of electronic components, such as logic gates, to implement control functions. The then existing CAD design tools were suitable for these first generation FPGA's.
Next generation FPGA's were subsequently developed which supported data path circuits. Data path circuits are circuits which manipulate data in groups. For example, some of the basic elements of data path circuits are accumulators, registers, memory, etc. For example, the Optimized Reconfigurable Cell Array (ORCA) FPGA, developed by AT&T, supports data path circuits in many ways. Each logic cell, called a Programmable Logic Cluster (PLC), can perform data manipulation operations on 4-bit data or a pair of 4-bit data. Each PLC contains fast carry logic for addition and substraction operations. This carry logic is also used when a PLC is used as a (4-bit) counter. Each PLC can be used as a 16.times.4 RAM. The routing structure supports 4-bit wide routing.
The existing CAD systems could not exploit the data path capabilities of the'second generation FPGA's because these CAD systems were geared toward random logic circuits and could not handle data path circuits well.